1. Technical Overview
This invention relates to a method for manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device. The invention includes a series of processes comprising an ion-implantation step followed by annealing process.
2. Background of the Invention
Recently, most computers and communication equipment have employed a large number of LSIs (large scale integrated circuit) in their core units, where many transistors and resistors are connected to form electrical circuits, integrated and formed into one chip. Therefore, the entire equipment performance depends on the performance of a single LSI unit. Higher integration enhancement improves the single LSI unit performance, and also achieves device down-scaling.
The device down-scaling can be accomplished by optimizing both an ion-implantation step, where a diffusion region, e.g. a source-drain diffusion region, is formed, and a subsequent annealing process. The means are available to produce an MOS transistor, having for example, a shallower source drain diffusion region than 0.2 .mu.m each.
In order to form a shallow diffusion region, it is required to use a low thermal exposure to not only distribute impurity atoms shallowly in the ion-implantation step, but also to prevent impurities from diffusing deeply in the subsequent annealing process. Thermal exposure is a function of both temperature and time.
However, if the thermal exposure budget is reduced, crystal defects occurring during manufacture can not be removed easily and remain therein.
On the other hand, according to the LSI defect analysis, the p-n junction leakage current is so high in a part of the cells that the charge retention characteristic may significantly deteriorate in a defective LSI. In many cases when the p-n junction leakage current is high, crystal defects due to dislocation are found.
Such crystal defects are frequently found in the vicinity of regions where various materials are buried in a semiconductor substrate, such as a trench capacitor and a trench isolation. In other words, if heterogeneity is buried in the semiconductor substrate, a heat stress occurs around the boundary between the heterogeneity and the semiconductor substrate as temperature rises or falls, because the rate of expansion for the semiconductor substrate differs from that of the heterogeneity.
The strength of a semiconductor substrate gradually decreases, whenever the semiconductor substrate is subjected to LSI processes. In order to examine the cause thereof, the inventor has observed how the mechanical strength of the Si substrate (Si substrate strength) and the maximum stress within the Si substrate (maximum stress within the Si substrate) change during LSI processes.
FIG. 1 shows experimental results, indicating the Si substrate strength and the maximum stress measured within the Si substrate in each process, when the LSI was manufactured according to the prior art manufacturing method. In FIG. 1, the horizontal axis denotes typical LSI processes sampled.
It is found in FIG. 1 that the maximum stress (solid line) within the Si substrate increases after the process to form the Si.sub.3 N.sub.4 or SiO.sub.2 layer by the CVD method, as well as after the annealing process following the ion-implantation step. At this time, the maximum stress within the Si substrate repeatedly increases and decreases, but does not show a monotones increase.
On the other hand, the Si substrate strength (dotted line) shows a nearly monotonous decrease, whenever the Si substrate is subjected to the process.
A slip or other defects, largely affecting the p-n junction characteristics, occur at points indicated by an arrow. As shown in FIG. 1., the maximum stress within the Si substrate exceeds the Si substrate strength at those points. In other words, plastic deformation occurs in the Si substrate, resulting in large defects at the time that the changing maximum stress within the Si substrate exceeds the decreasing Si substrate strength.
It is evident in FIG. 1 that a large decrease in the Si substrate strength appears in the ion-implantation step. The subsequent annealing process allows recovery of any implantation defects, and also increases the Si substrate strength to increase somewhat. In case of the second ion-implantation, a very little increase in the Si substrate strength appears after the annealing process.
The reason the Si substrate strength decreases is considered as follows.
In the ion-implantation, point defects (Frenkel defects) are formed within the Si substrate. The point defects can basically be recovered through the subsequent annealing process, but partly combine to cause dislocation.
Meanwhile, in fact point defects combine during the ion-implantation step, while larger defects (defect cluster) than point defects occur. The defect clusters have more stable energy than point defects, so they are seldom recovered through the annealing process after the ion-implantation, and tend to remain as a larger dislocation. Such a large dislocation decreases the Si substrate strength, as shown in FIGS. 2(a)-2(d).
FIG. 2 (a) shows a situation, where an As ion 33 is added into a non cooled or water cooled Si substrate 31 at about 3-5.times.10.sup.15 cm.sup.-2 and at acceleration voltage of about 20-40 keV. The beam current is about 10-20 mA. At this time, the temperature on the Si substrate 31 surface ranges from 25-60.degree. C. at ion-implantation.
Initial defects occurring through this ion-implantation are point defects, such vacancy and interstitial atoms which occur at the moment when an As ion is doped into the Si substrate. In addition, ion kinetic energy is partly converted into thermal energy, which is added to point defects.
As a result, vacancies and interstitial atoms can move slightly. Accordingly, recombination of vacancy and interstitial atoms allows point defects to be slightly recovered in the vicinity of the bottom of an ion-implanted layer, that means moderate state between an amorphous state and crystal state. At the same time, defect clusters due to vacancy inter-bonding, or defect clusters due to interstitial atoms inter-bonding are generated. On the other hand, ions implanted at locations of the tail (on the substrate side) region of the ion-implantation distribution easily diffuse into the interstice in the depth of the substrate even during ion-implantation, whereby defect clusters are also formed. As described above, the primary defects 32 are formed, consisting of defect clusters that have larger and more stable energy than point defects.
FIG. 2(b) shows a step, immediately after the said ion-implantation, wherein the annealing process is implemented for the Si substrate 31 in N.sub.2 atmosphere at 850.degree. C. for 30 minutes. The primary defects 32 are mostly recovered, as shown in FIG. 2(b). However, the secondary defects 34 larger than the primary defects 32, such as dislocation loops, is formed instead.
FIG. 2(c) shows a step wherein the second As ion-implantation is performed. As shown in the figure, the primary defects 32 are formed in the same manner as in the first As ion-implantation.
FIG. 2(d) shows a step wherein the second annealing process is implemented in N.sub.2 atmosphere at 850.degree. C. for 30 minutes. As shown in the figure, the primary defects 32 are recovered, but the secondary defects 34 are grown in larger secondary defects 34'.
According to the correlation between the Si substrate strength and these defects, the substrate strength decreases once when the primary defects 32 are formed by the first ion-implantation, but increases to such a degree that the primary defects 32 disappear by the subsequent annealing process.
Next, the primary defects 32 form again by the second ion-implantation so that the Si substrate strength remarkably decreases. The primary defects 32 are recovered by the subsequent annealing process. However, unlike the first ion-implantation, the existing secondary defects 34 form a core so as to form larger secondary defects 34' while the Si substrate strength slightly increases.
An additional stress larger than a certain level in this state inhibits the conversion of the substrate. Therefore, plastic deformation easily occurs and the defect grows to be a larger crystal defect, resulting in an increase in the p-n junction leakage current.
That is, there is such a problem that the repetition of an ion-implantation process and an annealing process results in a decreased Si substrate strength. Then, the stress causing plastic deformation in the Si substrate becomes smaller than the maximum stress within the Si substrate within a relatively short time. Further, the larger crystal defects occur, thereby increasing the p-n junction leakage current.
According to the conventional method as described above, the ion-implantation into the Si substrate followed by the annealing process cannot effectively decrease crystal defects within the Si substrate. In addition, as the ion-implantation and the annealing process are repeated, the Si substrate strength significantly decreases.
Japanese Kokai patent PH03-66122 discloses a method to cool a wafer stage during ion-implantation. Japanese Kokai patent PH04-162618 further discloses rapid annealing immediately after ion-implantation with cooled wafer stage. However, those prior art methods never provide a way to completely reduce crystal defects. Furthermore, those methods have a problem of H.sub.2 O remaining on a semiconductor substrate.
The purpose of the present invention is to solve the aforesaid problems and to provide a method for manufacturing a semiconductor device, which can prevent the mechanical strength of a semiconductor substrate from decreasing through ion-implantation process and the subsequent annealing process, as well as to provide a semiconductor device effective for the implementation.